Conventional electronic memories may be implemented by arrays of discrete memory cells. Each memory cell in an array may store a value. Many systems exist for writing a value to and reading a value from a memory cell.
FIG. 1A shows array 10 of memory cells 20, 25, 30 and 35 according to some conventional designs. In operation, a value may be written to node 21 of cell 20 by enabling write select line WSEL0 and by charging (or discharging) associated write bit-line WBL0 to the value while read select line RSEL0 and read bit-line RBL0 are high. During a read operation of cell 20, read select line RSEL0 is pulled low and read bit-line RBL0 discharges current to read select line RSEL0 through device 22. Device 22 conducts current from RBL0 to RSEL0 even if a “0” is stored at node 21 because the voltage corresponding to a stored “0” is greater than VSS for device 22.
FIG. 1B is a plot of a voltage on bit-line RBL0 during the read operation described above. It is assumed that read select line RSEL0 is pulled low at time t1. Line V1 shows the voltage on bit-line RBL0 in a case that a “1” value is stored at node 21, and line V0 shows the voltage on bit-line RBL0 in a case that a “0” value is stored at node 21. Line Vref shows the voltage on a reference bit-line that is also discharged during the read operation. A voltage differential exists between line V1 and line Vref and between line V0 and line Vref during a small window between time t1 and time t2. Since this difference varies based on whether a “1” or a “0” is stored at node 21, the stored value may be determined based on the difference between Vref and the actual voltage on bit-line RBL0 at a particular time during the read operation.
Whether a “1” or a “0” is stored, the bit-line voltage decreases to VCC−VTH before time t2. If VTH is large enough, other devices such as device 32 of memory cell 30 may turn on and transfer current from their associated read select line (RSELn in the case of memory cell 30) to the bit-line. These contention currents may clamp the bit-line voltage at VTH. The foregoing factors may adversely affect the development of the bit-line differential based on which the stored value is determined.